1. Field of the Invention
The present invention relates to charge coupled devices (CCD) typically used to capture color pictures in digital form, and more specifically to a method and apparatus for correcting the offset applied to the output of the CCDs.
2. Related Art
Charge coupled devices (CCDs) are often used to capture images received in the form of light. A CCD typically contains several pixels, with each pixel holding an amount of charge proportionate to the intensity of incident light and the length of time the light is allowed to fall on the pixel. The charge can be later translated to a voltage level and/or digital data for further processing and/or storing (in mass non-volatile storage). CCDs thus find application in devices such as digital cameras and scanners as is well known in the relevant arts.
A correction (termed xe2x80x9coffset correctionxe2x80x9d) is often applied to the output (i.e., voltage or digital data in the above paragraph) of a CCD typically to compensate for (or eliminate) undesirable components which may be present in the CCD output. For example, the charge generated by a CCD should ideally be entirely generated by the incident light but other phenomenon such as thermally generated electrons add to the charge.
Such additions are undesirable, for example, because a later reproduced image may be brighter than that represented by the light incident on the CCD. Accordingly, it is desirable that the undesirable components be eliminated, and the corresponding correction is termed as offset correction. The extent to which a correction is applied, is referred to as an offset, and the act of applying the offset to the CCD output may be referred to as offset correction. The difference between the applied offset and the accurate offset (which would have eliminated the undesirable components entirely) may be referred as an error in the offset correction.
To facilitate the removal of such undesirable components, CCDs often include black pixels which are shielded from light when the active pixels are exposed to light. The charge in the black pixels may be deemed to represent the undesirable components to some extent, and accordingly the offset to the CCD charge is computed based on the charge present in the black pixels. The offset is thus subtracted from the CCD outputs to generate the true image (close to the image represented by the incident light).
In one approach described in RELATED APPLICATION 1 noted above, the offset to be generated is indicated using two digital to analog converters (DACs) termed as coarse DAC (CDAC) and fine DAC (FDAC) respectively. The output voltage of the CDAC is subtracted from a voltage level representing the charge output of a CCD, and the resulting signal is amplified before further correction is performed based on the output of the CDAC. By choosing two DACs (instead of a single DAC), the CCD output may be corrected to a single bit precision of an ADC (used for digitizing the CCD output voltage), while minimizing the power and space consumption.
In effect, the output of CDAC effects correction in coarse steps (due to correction prior to amplification) and the output of FDAC effects correction in fine steps. Thus, the operation of CDAC leads to fast convergence to accurate offset correction while the FDAC allows correction potentially up to a least significant bit of a analog to digital converter (ADC) later used to convert the corrected CCD output to a digital representation. The correction may be switched between coarse correction mode and fine correction mode depending on the extent of further correction determined as the black pixels of the CCD output are continually examined.
One problem with such switching between two modes of correction is that the error in correction may suddenly jump as a result of the switch. A typical reason for such a jump is that the two DACs may generate different analog offsets for the same intended offset due to the inherent non-ideal implementations. The increase in error is undesirable at least in that it may manifest as a line (or a band) in a later reproduced image. Such display artifacts are generally undesirable. Accordingly, what is needed is a method and apparatus which provide for offset correction which converges rapidly, provides for accurate correction to a desired degree, while avoiding (or minimizing) display artifacts.
According to an aspect of the present invention, the correction to be applied to a previously applied offset is determined by an exponential curve which allows for a correction proportionate to an error in the offset (i.e., greater correction when error is large, and little correction when the error is small). As the correction is more when the errors are large, the offset may converge towards a correct value quickly.
In one embodiment, a correlated double sampler (CDS) receives the charge output of a charge coupled device (CCD), and corrects the output by an offset. The voltage generated by the CCD is amplified by a gain amplifier, and the amplified voltage is digitized by an analog to digital converter (ADC). An error determination circuit determines the error in the offset by examining the output corresponding to the black pixels. A correction circuit determines the correction to be applied to the offset by mapping the error to the exponential curve, and then generates a corrected offset value based on the determined correction.
According to another aspect of the present invention, the exponential curve is viewed as a sequence of connected linear segments, and the correction to the offset may be determined by the slope of the segment to which the error maps. As the slopes at large errors are steep, the slope is correspondingly high, and the offset converges towards the correct value quickly. Thus, the error is mapped to one of the segments and the correction is determined according to the slope. In an implementation, a look-up table generates an identifier of the segment, and a digital to analog converter (DAC) generates a corresponding correction value.
One more aspect of the present invention optimizes power consumption and space requirement by implementing the offset generation circuit using charge sharing in capacitors. One embodiment of the offset generation circuit contains a first capacitor and a first transistor. The source terminal of the transistor is connected to a constant current source, and the gate terminal is connected to the first capacitor. The offset generation circuit further includes a first block containing a plurality of sets, with each set in turn containing a second capacitor. The source terminal is connected to the second capacitor by a first switch. The first capacitor and the gate terminal is connected to the second capacitor by a second switch.
The first switch is closed and the second switch is opened to cause the second capacitor to be charged by a source voltage and the first capacitor to be charged by a gate voltage. The first switch is opened and the second switch is closed to short the first and second capacitors, whereby the change in voltage across the first capacitor is given by the equation: VSG/((1+(C1/C2)), wherein VSG represents the voltage across the source and gate terminals, and C1 and C2 respectively represent the capacitances of the first and second capacitors.
The capacitance of each of the second capacitors is chosen to enable different set to provide different changes, and the first and second switches corresponding to all the sets except a set designed to provide the desired change are maintained in an open position such that the desired change is attained on the first capacitor. By such a design, the voltage level on the first capacitor is continually updated as the black pixels of a CCD output are received. Thus, the voltage level on the first capacitor represents the corrected offset value.
Another feature enables the voltage on the first capacitor to be corrected positively and negatively (i.e., in both polarities). The first transistor may be implemented as an NMOS transistor. The offset generation circuit may further contain a PMOS transistor and a second block. The source terminal of the PMOS transistor also is connected to another constant current source and the gate terminal of the PMOS transistor is connected to the first capacitor.
The second block may have identical components as the first block, wherein the first and second switches of only one of the sets in both the first and second blocks is operated to be in a closed position such that the voltage level on the first capacitor is changed by one polarity if the operated set is in the first block and by another polarity if the operated set is in the second block. Thus, a decoder may cause only one of the sets to be operated depending on the sign and magnitude of the correction. As the offset generation circuit may be implemented in the form of capacitors, current sources and switches, the electrical power and space requirements may be minimized.